From the birth of the first integrated circuits at 1960, the number of devices on a chip has grown in an explosive increasing rate. The progress of the semiconductor integrated circuits has step into ULSI (ultra large scale integration) level or even higher level after almost four decades of developments. The capacity of a single semiconductor chip increases from several thousand devices to hundreds of million devices, or even billions of devices. Integrated circuits devices like transistors, capacitors, and connections must be greatly narrowed accompanying with the advancement. The increasing packing density of integrated circuits generates numerous challenges to the semiconductor manufacturing process. Every element or device needs to be formed within smaller area without influencing the characteristics and the operations of the integrated circuits. The demands on high packing density, low heat generation, and low power consumption devices with good reliability and long operation life must be maintained without any degradation in their functions. These achievements are expected to be reached with the simultaneous developments and advancements in the photography, the etching, the deposition, the ion implantation, and the thermal processing technologies, namely the big five key aspects of semiconductor manufacturing. The continuous increase in the packing density of the integration circuits must be accompanied with a shrinking minimum feature size. With present semiconductor manufacturing technology, the processes with a generally one-third micrometer in size is widely utilized. For making the next generation devices, the technologies focusing mainly on one-tenth micrometer or even narrower feature sizes are highly demanded.
Transistors, or more particularly the metal oxide semiconductor field effect transistors (MOSFET), are the most important and frequently employed devices in the integrated circuits with high performance. However with the continuous narrowing of device size, the sub-micron scale MOS transistors have to face so many risky challenges. As the MOS transistors become narrower and thinner accompanying with shorter channels, problems like the junction punchthrough, the leakage, and the contact resistance, cause the reduction in the yield and reliability of the semiconductor manufacturing processes.
For developing future MOS devices with a sub-micrometer or even smaller feature size, the ultra shallow junctions are required to suppress the short channel effects encountered with the down scaling sizes. In the work of Y. Nakahara et al. ("Ultra-shallow in-situ-doped raised source/drain structure for sub-tenth micron CMOS", Symposium on VLSI Technology Digest of Technical Papers, 1996 IEEE), the challenge in forming one-tenth micrometer MOSFET is disclosed. The requirement on ultra shallow junctions is proposed for suppress short channel effects while keeping parasitic resistance low to obtain high current derivability.
However, it is difficult to make the ultra shallow junction and form metal contact without degrading the device performance. In the article "0.15 .mu.m Delta-doped CMOS with On-field Source/Drain Contacts" proposed by K. Imai et al. in Symposium on VLSI Technology Digest of Technical Papers, 1996 IEEE, the problem is also addressed. The importance of the reduction in parasitic source/drain junction capacitance from the contacts is also emphasized especially for sub-micron CMOS (complementary metal oxide semiconductor) devices.